Method of manufacturing thin film transistor and method of manufacturing liquid crystal display device using the same

ABSTRACT

A method of manufacturing a thin film transistor includes: forming a gate insulating layer on a substrate having a gate electrode; forming a semiconductor layer of nanomaterial on the gate insulating layer; forming a source electrode and a drain electrode on the gate insulating layer; and applying a voltage to the source electrode and the drain electrode to arrange a direction of the nanomaterial.

This application claims the benefit of Korean Patent Application No. 2006-0124387 filed on Dec. 8, 2006, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates to a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor including a nanomaterial and a method of manufacturing a liquid crystal display device using the same.

2. Discussion of the Related Art

Recently, research for utilizing a nanomaterial such as a nanowire, a carbon nanotube, and a nanocable is actively under development. Therefore, a semiconductor layer can be formed of the nanomaterial.

The nanomaterial itself is formed of a crystal, such that its electron mobility is almost identical to that of a metal oxide semiconductor field effect transistor (MOSFET).

In the case where a thin film transistor is manufactured using the nanomaterial, the size of the thin film transistor can be minimized, so that a trend for the high degree of integration and miniaturization can be satisfied.

However, due to the lack of technology for arranging the nanomaterial until now, there is a limitation in manufacturing a nano thin film transistor.

Accordingly, it takes quite a manufacturing time to arrange the nanomaterial.

Thus, technology for easily arranging the nanomaterial is urgently needed.

Especially, the nanowire needs to be arranged with directionality to increases electron mobility. However, it is extremely difficult to form the nanowire with directionality through a present technological level.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a method of manufacturing thin film transistor and method of manufacturing liquid crystal display device using the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

An advantage of the present invention is to provide a method of manufacturing a thin film transistor capable of reducing a manufacturing time, and a method of manufacturing a liquid crystal display device using the same.

Another advantage of the present invention is to provide a method of manufacturing a thin film transistor capable of improving electron mobility.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will become apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purposed of the present invention, as embodied and broadly described, a method of manufacturing a thin film transistor includes: forming a gate insulating layer on a substrate having a gate electrode; forming a semiconductor layer of nanomaterial on the gate insulating layer; forming a source electrode and a drain electrode on the gate insulating layer; and applying a voltage to the source electrode and the drain electrode to arrange a direction of the nanomaterial.

In another aspect of the present invention, a method of manufacturing a liquid crystal display device includes: forming a gate electrode and a gate line on a substrate; forming a gate insulating layer on the substrate having the gate electrode; forming a semiconductor layer of nanomaterial on the gate insulating layer; forming a source electrode and a drain electrode on the gate insulating layer; applying a voltage to the source electrode and the drain electrode to arrange a direction of the nanomaterial; forming a passivation layer on the substrate having the source electrode and the drain electrode, the passivation layer having a contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer, the pixel electrode connecting to the drain electrode.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide further understanding of the invention and are incorporated in and constitute a part of this specification, illustrated embodiment(s) of the invention and together with the description serve to explain the principle of the invention.

In the drawings:

FIGS. 1A to 1H are views of manufacturing processes of a thin film transistor according to a first embodiment.

FIGS. 2A to 2E are views of manufacturing processes of a liquid crystal display device with a thin film transistor according to a second embodiment.

FIGS. 3A to 3H are views of manufacturing processes of a thin film transistor according to a third embodiment.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.

FIGS. 1A to 1H are views of manufacturing processes of a thin film transistor according to a first embodiment.

As illustrated in FIG. 1A, a first metal layer is deposited on a substrate 1, and then patterned to form a gate electrode 3.

Then, an insulating material is deposited on the substrate 1 having the gate electrode 3 to form a gate insulating layer 5.

As illustrated in FIG. 1B, a photoresist material is deposited on the gate insulating layer 5 and is exposed to remove the photoresist material corresponding to a region where a thin film transistor will be formed. Therefore, a photoresist pattern 7 is formed.

As illustrated in FIG. 1C, a self-assembled monolayer (SAM) material having a charge of a first polarity and an —NH2 group forms a SAM layer 9 on the substrate 1 having the photoresist pattern 7 through a gas reaction. The charge of the first polarity may be positive. The SAM layer 9 with a positive charge can pull a material having a negative charge and maintain a position of the pulled material.

As illustrated in FIG. 1D, the photoresist pattern 7 is stripped to leave the SAM layer 9 only on the region where the thin film transistor will be formed.

As illustrated in FIG. 1E, through a dropping apparatus such as a spuit, a nanomaterial 10 including nanowires with a second polarity is dropped into the region of the substrate I where the thin film transistor is formed. The nanomaterial 10 and the nanowires may have a negative polarity.

As illustrated in FIG. 1F, the nanomaterial 10 has a negative charge, and thus is pulled toward the SAM layer 9 with a positive charge, such that the nanowires 11 are formed on the SAM layer 9. Since the nanowires 11 on the SAM layer 9 are maintained by the SAM layer 9, they stay within the region where the thin film transistor is formed.

Since the nanowires 11 do not have directionality, the nanowires 11 on the SAM layer 9 are arranged in random directions. There may be a region where the nanowires 11 arranged in random directions may not contact each other. When the nanowires 11 are used as a semiconductor layer, charges may not move due to the region where the nanowires 11 do not contact each other, such that the thin film transistor does not operate. Additionally, since the nanowires 11 are arranged in random directions, charge mobility decreases.

To resolve the above limitation, the nanowires 11 are arranged with directionality through an electric field. Hereinafter, this will be described in more detail.

As illustrated in FIG. 1G, a second metal layer is deposited on the gate insulating layer 5 adjacent to the region where the nanowires 11 are formed, and then patterned to form a source electrode 13 a and a drain electrode 13 b. Although not illustrated, the source electrode 13 a and the drain electrode 13 b may be formed prior to forming the nanowires 11.

The first and second metal layers may include a least one of Cu, Al, AlNd, Mo, Cr, Ti, Ta, and MoW.

As illustrated in FIG. 1H, a predetermined voltage is applied to the source and drain electrodes 13 a and 13 b to form an electric field E between the source electrode 13 a and the drain electrode 13 b. The major axis of the nanowires 11 are arranged according to the direction of the electric field E generated between the source electrode 13 a and the drain electrode 13 b. The nanowires 1I1 between the source electrode 13 a and the drain electrode 13 b are arranged in the same direction. Accordingly, the nanowires 11 are arranged in one direction to have directionality.

Therefore, charges easily move through the nanowires 11, such that charge mobility drastically increases.

Additionally, since the nanowires 11 are arranged in the same direction, the nanowires 11 contact each other to allow charges to move, such that a thin film transistor normally operates and device characteristics can be improved.

A semiconductor layer is formed by the nanowires 11 with directionality.

The source and drain electrodes 13 a and 13 b are used as a supply source for a voltage used to generate the electric field E and a supply source of a signal in the thin film transistor.

That is to say, since the source and drain electrodes 13 a and 13 b, which are used to generate the electric field E, are not removed and remain as they are, they can become components of the thin film transistor. Accordingly, when the semiconductor layer becomes conductive due to a gate signal supplied to the gate electrode 3, a predetermined signal supplied to the source electrode 13 a passes through the semiconductor layer and is applied to the drain electrode 13 b.

Although not illustrated, the source and drain electrodes 13 a and 13 b may be removed and formed again as components of the thin film transistor.

FIGS. 2A to 2E are views of manufacturing processes of a liquid crystal display device with a thin film transistor according to a second embodiment.

The thin film transistor of FIGS. 2A to 2E may be manufactured using the same method as that of FIGS. 1A to 1H.

As illustrated in FIG. 2A, a first metal layer is deposited on a substrate 21, and then is patterned to form a gate electrode 23 and a gate line. The first metal layer may include a least one of Cu, Al, AlNd, Mo, Cr, Ti, Ta, and MoW.

A gate insulating layer 25 having an inorganic material such as SiNx and SiOx is formed on the substrate 21 having the gate electrode 23.

As illustrated in FIG. 2B, a semiconductor layer is formed using nanowires 29.

More specifically, a photoresist material is deposited on the gate insulting layer 25 first, and then is expose to uncover the gate insulating layer 25 corresponding to the semiconductor layer, such that a photoresist pattern (not shown) is formed.

A SAM material is formed on the substrate 21 having the photoresist pattern through a vapor phase reaction. The SAM material has a first polarity charge (e.g., a negative charge) and an —NH2 group.

After stripping the photoresist pattern, nanowires 29 are formed on the SAM layer 27 corresponding to the semiconductor layer by dropping nanomaterial including the nanowires 29. The nanomaterial has a second polarity charge (e.g., a positive charge) opposite to the first polarity charge.

As illustrated in FIG. 2C, a second metal material is deposited on the gate insulating layer 25 adjacent to the region where the nanowires 29 are formed, and then patterned to form a source electrode 31 a and a drain electrode 31 b, and a data line. The second metal material may include a least one of Cu, Al, AlNd, Mo, Cr, Ti, Ta, and MoW. Although not illustrated, the source electrode 31 a, the drain electrode 31 b and the data line may be formed prior to forming the nanowires 29.

Then, a predetermined voltage is applied to the source and drain electrodes 31 a and 31 b to form an electric field between the source electrode 31 a and the drain electrode 31 b. Accordingly, the nanowires 29 on the SAM layer 27 are arranged in one direction according to the direction of the electric field. Therefore, since the nanowire 29 have directionality, charge mobility drastically can be improved, and furthermore, because a non-contact region where the nanowires 20 do not contact each other is not formed, charge mobility is smoothly performed. Therefore, operational characteristics of a device can be improved.

A semiconductor layer is formed using the nanowires 29, which are arranged through the electric field.

As illustrated in FIG. 2D, a passivation layer including an inorganic layer such as SiNX, SiOx, etc. or an organic layer such as BCB, acrylic, etc. is formed on the substrate 21 having the source and drain electrodes 31 a and 31 b.

Next, the passivation layer 32 is etched to expose the drain electrode 31 b, such that a contact hole 33 is formed.

As illustrated in FIG. 2E, a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZ) is deposited, and then patterned to form a pixel electrode 35. The pixel electrode 35 may be connected to the drain electrode 31 b through the contact hole 33. The pixel electrode may be connected to the drain electrode 31 b via an intermediate layer.

Through the above processes, a liquid crystal display device with a thin film transistor, which includes a semiconductor layer formed by the nanowires 29, can be manufactured.

Accordingly, the liquid crystal display device arranges the nanowires 29, which are randomly arranged, in one direction by using an electric field. Therefore, charge mobility can be improved, and an operating speed of the thin film transistor can be increased. Furthermore, the thin film transistor normally operates without disconnection of the nanowires 29, such that operational characteristics of the thin film transistor can be improved.

FIGS. 3A to 3H are views of manufacturing processes of a thin film transistor according to a third embodiment.

The second embodiment is similar to the first embodiment. Accordingly, processes similar to those of the first embodiment will be briefly described in the description of the second embodiment.

As illustrated in FIG. 3A, a first metal layer is deposited on the substrate 1, and then patterned to form a gate electrode 3.

Next, an insulating material is deposited on the substrate 1 having the gate electrode 3 to form a gate insulating layer 5.

As illustrated in FIG. 3B, a SAM material having a charge of a first polarity and an —NH2 group forms a SAM layer 51 on the gate insulating layer 5 through a gas reaction. The charge of the first polarity may be positive.

As illustrated in FIG. 3C, after a mask 53 is arranged, a deep-ultraviolet (UV) irradiation is projected on the SAM layer 51.

As illustrated in FIG. 3D, the SAM layer 51 where the deep-UV is blocked by the mask 53 does not change, but the SAM layer 51 on which the deep-UV transmitted through the mask 53 is projected is photo-decomposed by the deep-UV. Accordingly, the SAM layer 51 is removed from all other regions except for the region where the semiconductor layer is formed.

As illustrated in FIG. 3E, a nanomaterial 10 including nanowires with a second polarity is dropped into the region where the thin film transistor is formed. The nanomaterial 10 with the nanowires may have a negative second polarity.

As illustrated in FIG. 3F, the nanomaterial 10 may have a negative charge, and thus is pulled toward an SAM layer 51 with a positive charge, such that the nanowires 11 are formed on the SAM layer 51. Since the nanowires 11 on the SAM layer 51 are maintained by the SAM layer 9, they stays within the region where the thin film transistor is formed.

The nanowires 11 on the SAM layer 51 are arranged in random directions.

As illustrated in FIG. 3G, a second metal layer is deposited on the gate insulating layer 5 adjacent to the region where the nanowires 11 are formed, and then patterned to form a source electrode 13 a and a drain electrode 13 b. Although not illustrated, the source electrode 13 a and the drain electrode 13 b may be formed prior to forming the nanowires 11.

As illustrated in FIG. 3H, a predetermined voltage is applied to the source and drain electrodes 13 a and 13 b to form an electric field E between the source electrode 13 a and the drain electrode 13 b. The major axis of the nanowires 11 are arranged according to the direction of the electric field E generated between the source electrode 13 a and the drain electrode 13 b. The nanowires 11 between the source electrode 13 a and the drain electrode 13 b are arranged in the same direction. Accordingly, the nanowires 11 are arranged in one direction to have directionality.

Therefore, charges easily move through the nanowires 11, such that charge mobility drastically increases.

Additionally, since the nanowires 11 are arranged in the same direction, the nanowires 11 contact each other to allow charges to move, such that a thin film transistor normally operates and device characteristics can be improved.

A semiconductor layer is formed by the nanowires 11 with the directionality.

The source and drain electrodes 13 a and 13 b are used as a supply source for a voltage used to generate the electric field E and a supply source of a signal in the thin film transistor.

That is to say, since the source and drain electrodes 13 a and 13 b, which are used to generate the electric field E, are not removed and remain as they are, they can become components of the thin film transistor. Accordingly, when the semiconductor layer becomes conductive due to a gate signal supplied to the gate electrode 3, a predetermined signal supplied to the source electrode 13 a passes through the semiconductor layer and is applied to the drain electrode 13 b.

Although not illustrated, the source and drain electrodes 13 a and 13 b may be removed and formed again as components of the thin film transistor.

The thin film transistor manufactured by the above manufacturing processes can be easily applied to a liquid crystal display device. The liquid crystal display device with the thin film transistor improves the mobility and operating speed of the thin film transistor, such that high-speed drive is possible. Additionally, the nanowires 11 are arranged in one direction in the liquid crystal display device, such that malfunctions of the thin film transistor can be prevented.

As described above, according to the embodiments, since the nanowires are arranged in one direction through the electric field, charge mobility can be improved. Additionally, an operating speed of the thin film transistors can also drastically increase.

Additionally, since the thin film transistor is manufactured using the nanowires, the size of the thin film transistors is reduced to satisfy the trend for the high degree of integrations and miniaturization.

According to the embodiments, since operational performance of the thin film transistor is enhanced, reliability for products can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. 

1. A method of manufacturing a thin film transistor, the method comprising: forming a gate insulating layer on a substrate having a gate electrode; forming a semiconductor layer of nanomaterial on the gate insulating layer; forming a source electrode and a drain electrode on the gate insulating layer; and applying a voltage to the source electrode and the drain electrode to arrange a direction of the nanomaterial.
 2. The method of claim 1, wherein the nanomaterial includes a nanowire.
 3. The method of claim 2, wherein a major axis of the nanowire is arranged according to a direction of an electric field between the source electrode and the drain electrode.
 4. The method of claim 1, wherein the step of forming the semiconductor layer of nanomaterial on the gate insulating layer includes: forming a self-assembled monolayer having a first polarity charge on the gate insulating layer; and dropping the nanomaterial on the substrate having the self-assembled monolayer, the nanomaterial having a second polarity charge.
 5. The method of claim 4, wherein the first polarity charge is positive and the second polarity charge is negative.
 6. The method of claim 4, wherein the self-assembled monolayer includes an —NH2 group.
 7. The method of claim 4, wherein the self-assembled monolayer is formed by vapor phase reaction.
 8. The method of claim 4, wherein the nanomaterial includes a nanowire having a position maintained by the first polarity charge of the self-assembled monolayer.
 9. The method of claim 8, wherein a major axis of the nanowire is arranged according to a direction of an electric field between the source electrode and the drain electrode.
 10. The method of claim 4, wherein the step of forming the self-assembled monolayer having the first polarity charge on the gate insulating layer includes: forming a photoresist pattern on the substrate having the gate insulating layer; forming the self-assembled monolayer having the first polarity charge on the substrate having the photoresist pattern; and stripping the photoresist pattern.
 11. The method of claim 4, wherein the step of forming the self-assembled monolayer having the first polarity charge on the gate insulating layer includes: irradiating the self-assembled monolayer to leave the self-assembled monolayer on a region where the semiconductor layer is formed.
 12. The method of claim 11, wherein the step of irradiating the self-assembled monolayer includes projecting a deep-ultraviolet irradiation.
 13. The method of claim 11, further comprising masking the irradiation corresponding to the region where the semiconductor layer is formed.
 14. The method of claim 11, wherein the irradiation photo-decomposes and removes the self-assembled monolayer.
 15. The method of claim 11, wherein the irradiation removes the self-assembled monolayer from regions except for the region where the semiconductor layer is formed.
 16. A method of manufacturing a liquid crystal display device, the method comprising: forming a gate electrode and a gate line on a substrate; forming a gate insulating layer on the substrate having the gate electrode; forming a semiconductor layer of nanomaterial on the gate insulating layer; forming a source electrode and a drain electrode on the gate insulating layer; applying a voltage to the source electrode and the drain electrode to arrange a direction of the nanomaterial; forming a passivation layer on the substrate having the source electrode and the drain electrode, the passivation layer having a contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer, the pixel electrode connecting to the drain electrode.
 17. The method of claim 16, wherein the nanomaterial includes a nanowire.
 18. The method of claim 16, wherein the step of forming the semiconductor layer of nanomaterial on the gate insulating layer includes: forming a self-assembled monolayer having a first polarity charge on the gate insulating layer; and dropping the nanomaterial on the substrate having the self-assembled monolayer, the nanomaterial having a second polarity charge.
 19. The method of claim 18, wherein the step of forming the self-assembled monolayer having the first polarity charge on the gate insulating layer includes: forming a photoresist pattern on the substrate having the gate insulating layer; forming the self-assembled monolayer having the first polarity charge on the substrate having the photoresist pattern; and stripping the photoresist pattern.
 20. The method of claim 18, wherein the step of forming the self-assembled monolayer having the first polarity charge on the gate insulating layer includes: projecting a deep-ultraviolet on a mask to leave the self-assembled monolayer on a region where the semiconductor layer is formed.
 21. The method according to claim 17, wherein a major axis of the nanowire is arranged according to the direction of an electric field between the source electrode and the drain electrode. 